FPGA Implementation of Viterbi Decoder using Trace back Architecture

Error correction is an integral part of any communication system and for this purpose, the convolution codes are widely used as forward error correction codes. For decoding of convolution codes, at the receiver end Viterbi Decoder is being employed. The parameters of Viterbi algorithm can be changed to suit a specific application. The high speed and small area are two important design parameters in today’s wireless technology. In this paper, a high speed feed forward viterbi decoder has been designed using track back architecture and embedded BRAM of target FPGA. The proposed viterbi decoder has been designed with Matlab, simulated with Xilinx DSP Tool, synthesized with Xilinx Synthesis Tool (XST), and implemented on Xilinx Spartan 3E based xc3s500e FPGA device. The results show that the proposed design can operate at an estimated frequency of 86.6 MHz by consuming considerably less resources on target device to provide cost effective solution for wireless applications. Keywords—DSP, FPGA, Matlab, Viterbi Decoder, XST